1. Field of Invention
The invention relates to a clock and data recovery circuit and a method thereof, and, in particular, to a clock and data recovery circuit including parallel control paths separated from each other and a method thereof.
2. Related Art
In the modern communication system, high-speed serial signal transmission gradually replaces the conventional parallel signal transmission. During the high-speed sequential signal transmission, the original low-speed parallel signal is converted into a high-speed serial signal to facilitate the transmission. Thus, a clock generating circuit is provided to generating a high-speed clock signal for sampling the high-speed sequential signal. And a clock and data recovery circuit is provided to recover the sampled high-speed serial signal at the receiving terminal. The clock and data recovery circuit is typically implemented with a phase-locked loop circuit, and compares the phase difference between a clock signal and the sampled high-speed serial signal, which is hereinafter referred to as the data signal. Thus, the self-calibrations of the clock signal and the data signal can be achieved, and the error rate of recovering the data signal may be reduced.
FIG. 1 is a block diagram showing a conventional clock and data recovery circuit 1. Referring to FIG. 1, the clock and data recovery circuit 1 includes a phase detecting circuit 11, a charge pump 12, a filter 13 and a voltage control oscillator 14. The phase detecting circuit 11 receives a data signal DATA and a local clock CLK, it compares a phase difference between the data signal DATA and the local clock CLK to generate two control signals UP, DN. The phase detecting circuit 11 is a bang-bang phase detector or a binary phase detector. The control signals UP, DN control one set of switches 121 in the charge pump 12 to turn on one set of current sources 122 such that the current I inputted to or outputted from the set of current sources 122 charges/discharges the filter 13 to generate an output voltage V. The output voltage V controls the voltage control oscillator 14 to adjust the phase of the local clock CLK such that the phase difference between the local clock CLK and the data signal DATA are held constantly. The filter 13 including a resistor 131 and a capacitor 132 filter the current I generated from the charge pump 12. The resistor 131 and the capacitor 132 are connected in series, and the other terminal of the capacitor 132 is grounded. In addition, the filter 13 further includes a capacitor 133 for suppressing the high frequency jitter. The other terminal of the capacitor 133 is also grounded. Usually, the capacitance of the capacitor 133 is much smaller than that of the capacitor 132, so the capacitor 133 is thus neglected in this case.
In the above-mentioned architecture, the voltage control oscillator 14 is mainly controlled by a single control path, which includes a proportional path and an integration path. The proportional path is the path of the current I flowing through the resistor 131. The integration path is the path of the current I flowing through the capacitor 132. In the proportional path, the current I provides a proportional gain directly proportional to the product of the current I and the resistance R related to the resistor 131. In the integration path, the current I provides an integration gain directly proportional to the ratio of the current I to the capacitance C related to the capacitor 132. A stability factor is defined as the ratio of the proportional gain to the integration gain. If the stability factor is higher, the system is more stable. In this case, the stability factor is equal to R×C . In order to obtain a better stability factor, the prior art usually increases the resistance R or/and capacitance C. If the resistance R is increased, the proportional gain and the voltage V are increased such that the voltage control oscillator 14 adjusts the local clock CLK more quickly. Therefore the phase of local clock CLK responses to the phase of the data signal DATA immediately. If the capacitance C is increased, the integration gain and the voltage V are decreased. It is therefore to prevent the voltage control oscillator 14 from adjusting the frequency of the local clock CLK too sensitively.
In summary of the proportional path and the integration path, the increased current I causes the proportional gain and the integration gain raise. Therefore the capacitance C is designed as larger for reducing the integration gain. On the contrary, the decreased current I causes the proportional gain and the integration gain reduce. Therefore the resistance R is designed as larger for raising the proportional gain. However, neither the larger resistance R nor the larger capacitance C is provided, it is costly for the clock and data recovery circuit 1.
In addition, the current I flowing through the single control path in the above-mentioned architecture simultaneously influences the proportional gain and the integration gain. Thus, the current I, the resistance R related to the resistor 131 and the capacitance C related to the capacitor 132 are not easy to adjust and design. The clock and data recovery circuit 1 is not easy to regulate and optimize, and its efficiency is hard to raise. Consequently, it is an important subject of the invention to provide a clock and data recovery circuit to solve the above-mentioned problems.